Startup shows 7 bit-per-cell Flash storage with 10 years of storage


One of the main driving forces to increase the capacity of the next generation of storage has been to increase the number of bits that can be stored per. cell. The easy jump of one to two bits-per-cell provides an equal 100% increase, in return for more control needed to read / write bits, but also limits cell endurance. We have seen commercialization of storage up to four bits per second. cell, and speaks of five. A Japanese company is now ready to start talking about their new 7-bit-per-cell solution.


Image lent by Plextor, up to 4 bits per cell

Moving from one to two bits-per-cell provides an easy doubling of capacity, and moving to three bits-per-cell is only a 50% increase. As more bits are added, the value of adding these bits decreases, but the cost of the equipment to control reading and writing increases exponentially. There must be an intermediate balance between how many bits-per-cell make economic sense and how much the control electronics cost to implement to activate these bits.

  • 1 bit pr. cell requires detection of 2 voltage levels, base capacity
  • 2 bit pr. cell requires detection of 4 voltage levels, + 100% capacity
  • 3 bit pr. cell requires detection of 8 voltage levels, + 50% capacity
  • 4 bit pr. cell requires detection of 16 voltage levels, +33% capacity
  • 5 bit pr. cell requires detection of 32 voltage levels, +25% capacity
  • 6 bit pr. cell requires detection of 64 voltage levels, +20% capacity
  • 7 bit pr. cell requires detection of 128 voltage levels, +16.7% capacity

The more bits-per-cell, the lower the endurance – the voltage variation when you store many bits only has to slide a little to get the wrong result, and then repeated readings / writes to a high-capacity cell will cause that voltage drift to operate until the cell is useless . Right now, the market seems content with three bits-per-cell (3bpc) for performance and four bits-per-cell (4bpc) for capacity, with a few 2bpc designs for long-lasting endurance. Some of the big vendors have been working on 5bpc storage, though the low endurance might only make the technology good for WORM – write once, read many, which is a common acronym for what looks like something like an old-school CD or non-rewritable DVD.

Floadia Corp., a Series C startup from Japan, issued a press release this week to state that they have developed storage technology capable of seven bits-per-cell (7bpc). Still in the prototype stage, this 7bpc flash chip, probably in a WORM scenario, has an effective 10-year storage time for the data at 150C. The company says that a standard modern memory cell with this level of control would only be able to retail the data for about 100 seconds, and so the secret of the design is to do with a new type of flash cell they have developed.

The SONOS cell uses a distributed charge trap design that relies on a silicon oxide nitride oxide silicon layout, and the company points to an efficient silicon nitride film in the center where the charges are trapped to allow high retention. In simple voltage programs and erase cycles, the company presents 100k + cycles with a very low voltage operation. The oxide-nitride oxide layers are dependent on SiO2 and Si3N4, the latter of which are claimed to be easy to manufacture. This makes it possible to use a non-volatile SONOS cell in NV-SRAM or embedded designs, such as microcontrollers.

It’s actually the last point which means we’re a long time from seeing this in modern NAND flash. Floadia is currently partnering with companies like Toshiba to implement the SONOS cell in a range of microcontrollers, rather than large NAND flash deployments, on the 40nm process node as embedded flash IP with compute-in-memory capabilities. These are not yet at 7 bits per second. cell, which means that the company promotes that two cells can store up to 8-bit network weights for machine learning end – when we reach 8 bits per. cell, then it may be more useful. The 10-year storage of the cell data is where it gets interesting, as embedded platforms will use fixed-weight algorithms over the life of the product, except perhaps the infrequent update. Even with increased longevity, Floadia does not go into detail about the cyclability at 7bpc at present.

An increase from modern 3bpc to 6bpc NAND flash would provide a double density increase, but larger cells would be needed, which would negate the benefits. There is also the performance aspect if the development of> 4bpc ever reached consumers, which has not been affected.

It will be an interesting technology to follow.

Source: Floadia press release



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